The yield of an integrated circuit is directly related to the profitability of a product, and that increasing yield by even a few percentage points may save a company millions of dollars. It is well known that integrated circuit manufacturing processes have inherent variations that cause the performance of a design to vary from one chip to another. A product's yield is the percentage of manufactured designs that pass all performance specifications.
The yield of an integrated circuit is the ratio of the number of chips that meets specifications in certain conditions to the total number of chips that are manufactured. There are two types of yield. One type is referred to as the functional field, which measures percentage of chips that meet the intended functionality. The other type is referred to as the parametric yield, which measures percentage of chips that meet all specifications. To maximize the parametric yield of an integrated circuit design, two classes of effects need to be considered. One class is the environmental effect, which includes temperature changes, power supply changes, etc. The other class is the manufacture-related effect, which is also referred to as the physical process variation. In general, the methodology to design a robust integrated circuit to account for the environmental changes and process variations is called design-for-yield (DFY) or design-for-parametric yield.
The physical process variation is caused by processing and masking imperfection. Normally it is modeled as two different types of statistical variations in circuit device model: 1) global variation or inter-die variation; and 2) local variation or intra-die variation. Design-for-yield (DFY) has becoming more and more important for high performance analog circuit design as the semiconductor processing technology approaches smaller sub-micron geometry. This is because the variation of device property, especially mismatch effects, increases as the device size shrinks to submicron processing technology. Designing an analog circuit to a 90 nm or newer processing technology would require more design effort to achieve a high yield. To solve this problem, there are various conventional methods that consider environmental and physical variations to optimize analog circuit yield.
One approach is the worst-case corner method. This method is limited for the following reasons. First, unlike most digital circuits, the typical analog circuit has many varied performance specifications and requires a richer set of simulations to qualify. The simple “fast” device and “slow” device worst-case corner methods are not adequate for analog circuits. Second, within-die variations (mismatch variations) are becoming more important than die-to-die variations (global process variations) for high performance analog circuits in deep-submicron technologies. The number of worst-case corners increases exponentially with the number of parameters that are varied. Thus, simulating worst-case corners can quickly become infeasible in determining mismatch effects. Furthermore, the worst-case corner method does not typically consider the distribution of parameters and the correlation information between the parameters. Consequently, an integrated circuit designed using this method often turns out to be either over-constrained or under-constrained, and therefore is not optimized in terms of cost and performance.
Another conventional approach is the response surface model (RSM) method. In this approach, response surface models can be built for both design variables and statistical variables to accelerate yield estimation and to maximize yield as part of the design methodology. The process of building RSMs includes model training, model selection, and model testing. Model training is a process to adjust model parameters to minimize model training error. Model selection is the process to select a corresponding model structure and complexity for a particular design. Model testing is a process to evaluate the quality of the model. The RSM method has high accuracy in low dimensional and weak nonlinear design space. The yield estimation process can be accelerated by running Monte Carlo simulations on RSM. By applying direction optimization techniques on some forms of RSM makes design-for-yield process easier. For examples, quadratic optimization can be used to find the optimum RSM. However, most analog designs are nonlinear. It is difficult to screen statistical and design variables. Thus, the number of samples to build RSM grows rapidly as the number of variables increase. Also, the error of the RSM method may lead to inaccurate yield estimation, which is another drawback of this approach.
Yet another convention approach is the worst-case distance (WCD) method. This method is illustrated as follows. First, assume there is a linear relationship between performance ƒ and statistical variable s, and assume there is a Gaussian distribution for statistical variable s. For performance function ƒ(s), the performance specification is U. In this approach, the performance variance is first computed. Then, the worst-case distance βW is calculated. The yield can then be estimated by using the worst-case distance βW for each performance. Next, the Worst-case parameter and tolerance class is derived. For the nonlinear circuit performance, sensitivity analysis is used for each performance and it iterates the worst-case distance process until the design converges. A drawback of this approach is that nonlinear circuit performance may not follow the Gaussian distribution, thus the yield estimation may be prone to error. Since sensitivity analysis has limitations for the nonlinear performance function, this method is useful for linear or nearly linear performance functions with a small number of statistical variables, and it is less useful for nonlinear performance specifications or for designs with a large number of parameters.
Therefore, there is a need for a method and system that maximize the yield of an integrated circuit in light of the manufacturing process variations. In particular, there is a need for an effective search process for finding design points that meet the design specifications and at the same time produce high yield in manufacturing.